Running again....

Yes, the board is up and running again. This time the VIA's work as expected =) Great since I now have the RTC working properly.

The graphic controller is coming along. I have been writing some more detailed chapters in the specification for the playfield generator. What I am looking right now is a 3-layer tile generator with soft scroll capabilities. This would allow me to have a static background and as well as two layers of background objects that could move on top of the background. This can be used to create the illusion of having mountains moving in the background or multiple levels of starfields. Good for nice platform or arcade type action games. Of course, on top of that you will have the sprites to create characters to interact with.

Right now I'm looking at a solution where the graphic memory is local to the graphic controller. That means the host CPU will not be able to directly access this memory. This has both advantages and disadvantages but in this case the advantages outweigh the disadvantages. The host CPU will have to "download" the tile sets as well as the tile map to the playfield memory. The playfield memory is 128Kbyte and holds both the tile sets as well as the tile maps. There are a number of registers in the gfx controller that defines the tile sets. Each tile layer has 5 registers associated with it.

1. Tile Window Base Address (TWBA)
   
2. Tile Map Length (TML)
   
3. Soft Scroll X (SSX)
   
4. Soft Scroll Y (SSY)
5. Tile Set Base Address (TSBA)
   

The tile generator works so that a window of 40x30 tiles is moved over the tile map, allowing the viewer to see different parts of the tile map. The base address (TWBA) points to the first tile (top left corner) of the window. The Tile Map Length (TML) register then defines how long (in bytes) the map is, this is essentially how many bytes that the controller adds to the map to get the next line of information from the tile map. The soft scroll registers defines how many pixels the controller should move the window to the right (SSX) or down (SSY). Every tile layer has one tile set associated with it and the TSBA register points to where in the memory this tile set is found.

The tile layers work independently which means that they can share the same tile map or have a unique tile map and tile set.

This is the basis for what I will be starting to experiment with. The system will be designed around a time slotted mechanism for retrieving data from the gfx memory. When implementing the sprite mechanisms it will be built around the same core for obtaining its data.

That's all for now folks.

More bloopers and more..

Hrrmm, seems I forgot to connect the reset signal to my VIA's. This is highly discouraging as it seem I am not the total genius after all (and everyone smirks =). Anyway *hehe* will fix it later tonight.

Today has been a really sweeet day. Watching SG-1 and coding 6502 assembly alternatively. Really makes life worth living =)

Nops, gotta go, back to the lab.

Problem in Eden

When trying to do serial IO using Rx interrupts I noticed a design flaw in my schematic. This was the first patch on my PCB which isn't to bad, considering its me =)

I also found one unsoldered ground connection on one of the 6116 SRAMs.

So after extensive testing of the board I am quite convinced that all subsystems are working as expected. During the debug process I have decided that the board needs a few tweaks for the final revision. Nothing major but still......

Graphic game control FPGA

The specs for my graphical controller is beginning to take form. The current basic specs are outlined as follows.

• Fixed resolution 320 x 240 pixel.
• 4/8 bit color depth.
  
• 32 8-bit palette registers.
• 3-layer tile based playfield controller.
• 8 x 8 tile size.
• Flexible sprite controller.
• 64 sprites per frame.
• 16 sprites on each scan line.

More information will follow shortly.......

Up and running

The CPU board is up and running, EhBasic works properly and both VIA's can be accessed correctly with peek and poke commands. The interrupt system also seem to be working as expected. If I enable interrupts from the ACIA they are received and can be processed properly. I have no reason to think that the VIA interrupts would not work. I did change to a 65C02 processor in order to not have to rewrite the monitor software. Oh well, it seem to work properly as well.


Next thing on schedule for my computer system is a graphic controller for gaming and visual presentation. This will be done with an FPGA system to allow for some fancy layering and sprite capabilities.

Stay Tuned.........

New 6502 based system

The CPU board for the retro system I am working on is coming along just fine. The chip selects for the 6116 SRAMs has been confirmed to work as expected. The control signals for the FLASH memory also works as expected (since the test program can execute =). I have not tested the VIA's or the ACIA yet.

Next step is to port in a monitor software and EhBasic in order to fully verify the functionality of the CPU board.

More to follow......

Alien Computers !?

I was just watching an episode of Stargate SG-1 and reacted when the Aasgard guy Thor referred to a computer as a..... "computer". I would have assumed that another race, from another planet would have another name for the.... eh computer. Oh well never mind =)